The present invention relates to a method for producing a silicon wafer of high resistivity and high gettering ability wherein a silicon wafer produced by the Czochralski method is subjected to a heat treatment, and a silicon wafer having such characteristics, as well as a method for producing a silicon wafer wherein generation of slip dislocations, which are likely to be generated in a heat treatment process such as one in a device production process, can be suppressed, and a silicon wafer having such characteristics.
Silicon wafers of high resistivity produced by the floating zone method (FZ method) have conventionally been used for power devices such as high-voltage power devices and thyristors. However, it is difficult to produce a silicon wafer having a diameter of 200 mm by the FZ method, and it is impossible to produce one having a diameter of 300 mm or more by currently used techniques. Further, the planar resistivity distribution of usual FZ wafers is inferior to that of CZ wafers with respect to both of the macroscopic resistivity distribution and the microscopic resistivity distribution. As a method for improving this situation, there is a method utilizing neutron irradiation. However, this method can produce only N-type wafers, and moreover suffers from a drawback that increased cost is invited.
On the other hand, by the Czochralski method (CZ method), wafers of excellent planar resistivity distribution can be produced. In addition, wafers of a large size having a diameter of 200 mm or 300 mm are already produced by this method, and it is considered to be well possible to produce those having a diameter of about 400 mm or more. Therefore, silicon wafers produced by the CZ method will be promising in the future.
In particular, recent semiconductor devices for mobile communications and the latest C-MOS devices require decrease of parasitic capacity, and for this reason, silicon wafers of a large diameter and high resistivity are required. Further, there has been reported the effect of use of a high resistivity substrate on signal transmission loss or decrease of parasitic capacity in Schottky barrier diodes. Therefore, there is required a method for producing wafers of high resistivity (at least 100 xcexa9xc2x7cm) by the CZ method.
Furthermore, in order to obtain such semiconductor devices as mentioned above with still higher performance, the so-called SOI (Silicon On Insulator) wafers may be used. As a representative method for producing such SOI wafers, there is the wafer bonding method. This method comprises a step of bringing a bond wafer, which serves as a device forming layer, into close contact with a base wafer, which serves as a support substrate, via an oxide film, a step of subjecting them to a heat treatment so that the both should be firmly bonded, and a step of making the bond wafer into a thin film as an SOI layer. As also for the case where semiconductor devices are produced by using bonding SOI wafers produced by such a method, it is required to use wafers of high resistivity produced by the CZ method as base wafers in order to solve the problems such as the production of wafers of a large diameter and the signal transmission loss.
However, since the CZ method utilizes a crucible made of quartz, not a small amount of oxygen (interstitial oxygen) is introduced into a silicon crystal. Although such oxygen atoms are usually electrically neutral when they exist alone by themselves, if they are subjected to a heat treatment at a low temperature of around 350 to 500xc2x0 C., a plurality of them gather to release electrons and become electrically active oxygen donors. Therefore, if a wafer obtained by the CZ method is subsequently subjected to a heat treatment at about 350 to 500xc2x0 C. in the device production process and so forth, it may suffer from a problem that resistivity of a high resistivity CZ wafer is reduced due to the formation of the oxygen donors.
One of the methods for preventing the resistivity reduction due to the above oxygen donors and obtaining a silicon wafer of high resistivity is the method for producing a silicon single crystal having a low interstitial oxygen concentration from an initial stage of the crystal growth.
Japanese Patent Publication No. 8-10695 discloses that, as a method for producing a wafer of high resistivity by the CZ method, a silicon single crystal having a high resistivity of 1000 xcexa9xc2x7cm or higher can be produced by preparing a silicon single crystal of a low interstitial oxygen concentration through the magnetic field applied CZ method (the MCZ method). Further, Japanese Patent Laid-open Publication No. 5-58788 discloses that a silicon single crystal can be produced with a high resistivity of 10000 xcexa9xc2x7cm or higher by performing the MCZ method using a synthetic quartz crucible.
As another method for producing wafers of a high resistivity by the CZ method, there has also been proposed a method conversely utilizing the phenomenon of the oxygen donor formation, wherein a P-type silicon wafer of a low impurity concentration and low oxygen concentration is subjected to a heat treatment at 400 to 500xc2x0 C. to generate oxygen donors, and P-type impurities in the P-type silicon wafer is compensated by these oxygen donors so that the wafer should be converted into N-type to produce an N-type silicon wafer of high resistivity (Japanese Patent Publication No. 8-10695).
However, a silicon single crystal of a low interstitial oxygen concentration produced by the MCZ method or the like as mentioned above suffers from a drawback that the density of bulk defects generated by a heat treatment in the device production process becomes low, and sufficient gettering effect will be unlikely to be obtained. In devices of a high integration degree, it is essential to impart gettering effect by a certain amount of oxygen precipitation.
Further, the method of obtaining a silicon wafer of high resistivity by generating oxygen donors by a heat treatment and compensating P-type impurities in the wafer to convert it into N-type is a complicated method that requires accurate control of initial resistivity (concentration and kind of impurities) and heat treatment time, and a heat treatment for a long period of time. Moreover, this method cannot provide P-type silicon wafers of high resistivity. In addition, resistivity of wafers obtained by this method may also vary depending on a subsequent heat treatment. Furthermore, in this method, if a high interstitial oxygen concentration is used, it becomes difficult to control the wafer resistivity. Therefore, this method suffers from a drawback that a low initial concentration of interstitial oxygen in a silicon wafer must be used, and the gettering effect of the wafer becomes low.
While semiconductor devices for mobile communications or the latest C-MOS devices require silicon wafers of a large diameter and high resistivity produced by the CZ method as described above, integrated circuits such as usual LSI are also produced with silicon wafers mainly produced by the CZ method and having a usual resistivity (about 1-20 xcexa9xc2x7cm) and through a production process comprising a large number of production steps including several heat treatment steps other than the aforementioned heat treatment of the device production process. These heat treatment steps are very important steps, in which performed are, for example, formation of an oxide film on a wafer surface layer, diffusion of impurities, formation of denuded zone and gettering layer and so forth.
As a resistance heating type heat treatment furnace for a so-called batch processing, which is used for the aforementioned heat treatment process and can simultaneously anneal a plurality of wafers, there are a horizontal type furnace and a vertical type furnace. In the horizontal type furnace, wafers are loaded into the furnace while they are vertically held on a jig for holding wafers, called a boat, and subjected to a heat treatment. In the vertical type furnace, wafers are loaded into the furnace while they are horizontally held on a boat, and subjected to a heat treatment.
As one of problems observed in heat treatments of the aforementioned both types, generation of slip dislocation is mentioned. Slip dislocations are defects caused by deformation of crystals due to slippage of the crystal caused by thermal stress in the heat treatment process, which forms steps on wafer surfaces. If such slip dislocations are generated on the wafer surfaces, not only the mechanical strength of the wafers is degraded, but also the device characteristics are adversely affected, for example, junction leakage is caused. Therefore, it is desirable that they should be reduced as far as possible.
If a heat treatment is carried out by using a heat treatment furnace of the aforementioned batch processing type, temperature distribution will be generated within a wafer plane during loading and unloading of wafers into or from the heat treatment furnace and temperature increase or decrease in the furnace. This temperature distribution generates stress. Then, when this stress exceeds a certain critical value, slip dislocations are generated. In this case, since wafers are placed on a boat, the weight of the wafers is likely to be concentrated at a portion where they are in contact with the boat. Therefore, the stress applied to the contact portion becomes large, and slip dislocations become likely to be generated. In particular, if the diameter of wafers becomes large, the weight of wafers becomes large and therefore its influence becomes serious.
On the other hand, other than the aforementioned heat treatment furnace of batch processing type, an RTA (Rapid Thermal Annealing) apparatus, which is a heat treatment furnace of single wafer processing type and utilizes lamp heating or the like, may be used for the heat treatment process. An apparatus of this type performs single wafer process, shows extremely high temperature increasing and decreasing rates, and is unlikely to cause temperature distribution within a wafer plane compared with a batch type furnace. Therefore, it is particularly effective for heat treatment of wafers of a large diameter. However, like a batch type heat treatment furnace, an apparatus of this type also suffers from the phenomenon that stress due to the weight of wafers is concentrated on the contacting portion with the jig for holding the wafers, and thus slip dislocations are likely to be generated.
In order to suppress the generation of such slip dislocations, improvement has been attempted so far mainly from two kinds of aspects. One of them is an attempt to reduce the stress applied on the contacting portion of wafers and boat, in which it is attempted to suppress the concentration of the stress by improving a shape of the boat. For example, in the technique disclosed in Japanese Patent Laid-open Publication No. 9-251961, the concentration of the stress is obviated by using plane contact, not point contact, between the wafers and the boat, which plane contact is obtained by using a vertical type heat treatment boat having an angle of a portion for holding the wafer corresponding to deflection of the wafers caused by the weight of the wafers.
Another aspect consists of reduction of the temperature distribution within the wafer plane generated during the heat treatment process, and the reduction is realized by improvement of the heat treatment conditions. For example, in the technique disclosed in Japanese Patent Laid-open Publication No. 7-235507, hydrogen or helium, which has higher thermal conductivity compared with nitrogen and argon usually used for temperature increase and decrease, is used to activate the conduction of heat into the wafers so that temperature difference within a wafer plane should be reduced. Further, Japanese Patent Laid-open Publication No. 7-312351 proposed prevention of the generation of slip dislocations by lowering temperature increasing and decreasing rates as the temperature becomes higher.
As approaches based on these two kinds of aspects, there are known a number of techniques other than those exemplified above. Although these approaches are effective in some degree concerning prevention of slip dislocations during the heat treatment process, they cannot necessarily be considered sufficient means for all of the various heat treatment processes used in the device production process, and some may have difficulty concerning the cost for practical use.
Other than the aforementioned two kinds of approaches for suppressing the generation of slip dislocations, it has also been attempted to improve the anti-slip property from the viewpoint of oxide precipitates in wafers. For example, Japanese Patent Laid-open Publication No. 9-190954 describes that, as for CZ wafers of low oxygen concentration, the generation of slip dislocations can be suppressed if polyhedral oxide precipitates are formed at a predetermined density within a region covering a distance of 10 mm or less from the periphery of wafer, in which slip dislocations are likely to be generated. Furthermore, it disclosed a technique comprising implanting oxygen ions into the region covering a distance of 10 mm or less from the periphery and subjecting the wafer to a two-step heat treatment in a nitrogen atmosphere in order to generate oxide precipitates at a predetermined density.
Further, from the viewpoint of the problem that slip dislocations are generated from oxide precipitates themselves when thermal compressive stress is applied to a wafer containing the oxide precipitates, Japanese Patent Laid-open Publication No. 10-150048 proposed a wafer containing carbon at a predetermined concentration as a wafer in which slip dislocations are unlikely to be generated even under a thermal compressive stress with which slip dislocations may be normally generated.
As explained above, the conventional techniques suffer from a problem that, when a silicon wafer produced by the CZ method (it may be referred to simply as a xe2x80x9cCZ silicon waferxe2x80x9d or xe2x80x9cCZ waferxe2x80x9d for the present invention) is subjected to a heat treatment during the device production process, for example, for formation of oxide film, diffusion of impurities, formation of denuded zone or gettering layer and so forth, the characteristics of wafers may be adversely affected (reduction in resistivity, generation of slip dislocations etc.).
That is, among the conventional techniques, there are no means for obtaining a CZ wafer of high resistivity that does not suffer from the problem of reduction in resistivity due to the generation of oxygen donors and shows high gettering effect, even when the silicon wafer produced by the Czochralski method is subjected to a heat treatment. Thus, it has been desired to develop a method satisfying these requirements.
Further, as for suppression of slip dislocations during the heat treatment process, the techniques disclosed in the above Japanese Patent Laid-open Publication Nos. 9-190954 and 10-150048 are techniques for improving characteristics of wafers themselves, and therefore they may be effective for any heat treatment process. However, both of them are not practical techniques. That is, the technique of Japanese Patent Laid-open Publication No. 9-190954 requires additional steps of ion implantation and the two-step heat treatment. Further, in the technique of Japanese Patent Laid-open Publication No. 10-150048, since carbon is added at a predetermined concentration, there is anxiety for adverse effect of carbon on the device characteristics.
Furthermore, there is also a problem that, when an epitaxial wafer is produced by depositing a single crystal silicon layer on a silicon wafer through epitaxial growth, defects such as slip dislocations are generated during the epitaxial process at a high temperature, thereby the yield of the epitaxial process is degraded and the characteristics of devices eventually produced are also degraded.
The present invention was accomplished in view of such problems, and its first object is to provide a method for obtaining a CZ wafer exhibiting high resistivity and high gettering effect while preventing the reduction of resistivity due to the generation of oxygen donors, a CZ wafer of high resistivity produced by the method, and an SOI wafer using this wafer.
The second object of the present invention is to provide a CZ silicon wafer in which the anti-slip property of a portion to be contact with a heat treatment boat of the silicon wafer to be subjected to a heat treatment process is improved and there are substantially no slip generated from oxide precipitates themselves through a relatively simple practical method.
A further object of the present invention is to provide an epitaxial wafer in which slip dislocations are not generated and high resistivity and gettering effect are attained.
In order to achieve the aforementioned first object, the present invention provides a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having a resistivity of 100 xcexa9xc2x7cm or more and an initial interstitial oxygen concentration of 10 to 25 ppma by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to an oxygen precipitation heat treatment so that a residual interstitial oxygen concentration in the wafer should become 8 ppma or less.
If a silicon wafer of high oxygen concentration having a high resistivity of 100 xcexa9xc2x7cm or more and an initial interstitial oxygen concentration of 10 to 25 ppma (JEIDA: Japan Electronic Industry Development Association) is produced by the Czochralski method, and this high resistivity CZ wafer is subjected to an oxygen precipitation heat treatment so that a residual interstitial oxygen concentration in the wafer should become a low oxygen concentration of 8 ppma or less, as described above, interstitial oxygen in the silicon wafer can be precipitated to prevent them from becoming electrically active oxygen donors, and thereby the reduction of resistivity of the wafer can be prevented. In addition, this method provides a high density of oxide precipitates, and therefore the gettering effect can also be enhanced. Moreover, in this method, since the silicon wafer is produced by the CZ method, the diameter of the wafer can easily be made larger.
The present invention further provides a silicon wafer produced by the aforementioned production method. A silicon wafer produced as described above is a silicon wafer which is produced by subjecting a silicon wafer having a resistivity of 100 xcexa9xc2x7cm or more and an initial interstitial oxygen concentration of 10 to 25 ppma to an oxygen precipitation heat treatment and has a residual interstitial oxygen concentration of 8 ppma or less.
In the silicon wafer of the present invention, the amount of residual interstitial oxygen, which becomes electrically active oxygen donors, is small as described above, but there are sufficient oxide precipitates in the bulk portion. Therefore, it can be a silicon wafer having both of high resistivity and gettering effect.
The silicon wafer of the present invention further can be a silicon wafer having a resistivity of 100 xcexa9xc2x7cm or more and an initial interstitial oxygen concentration of 10 to 25 ppma, and maintaining resistivity of 100 xcexa9xc2x7cm or more after a device production heat treatment at 350 to 500xc2x0 C.
Thus, this silicon wafer of the present invention is a wafer of which resistivity is maintained to be 100 xcexa9xc2x7cm or more after the wafer is subjected to a heat treatment for device production at 350 to 500xc2x0 C., because the generation of oxygen donors is suppressed, in spite of the fact that it has a high resistivity of 100 xcexa9xc2x7cm or more and a high oxygen concentration of 10 to 25 ppma as the initial interstitial oxygen concentration. That is, the wafer can be a silicon wafer having both of high resistivity and high gettering effect.
The term xe2x80x9cdevice production heat treatmentxe2x80x9d is used herein to collectively refer heat treatments used in the device production process such as electrode wiring process, after the wafer is subjected to a gettering heat treatment and other treatments.
Further, the aforementioned silicon wafers of the present invention can be a silicon wafer having a bulk defect density of 1xc3x97108 to 2xc3x971010 defects/cm3 after a gettering heat treatment or a device production heat treatment.
The above silicon wafer having a bulk defect density of 1xc3x97108 to 2xc3x971010 defects/cm3 after a gettering heat treatment or a device production heat treatment can be a silicon wafer having nuclei that can be origins of oxide precipitates in the wafer, that is, oxygen precipitation nuclei, at a level considered necessary as gettering sites, i.e., a density of oxide precipitates as bulk defects of 1xc3x97108 to 2xc3x971010 defects/cm3, in spite of the fact that it is a high resistivity wafer, and thus it is a silicon wafer that does not exist so far.
The term xe2x80x9cgettering heat treatmentxe2x80x9d is used herein to collectively refer to heat treatments used after the processing of the grown silicon single crystal ingot into a wafer and before the device process, and they mainly aim at elimination of crystal defects present in a portion near a surface by out-diffusion of impurity oxygen.
The present invention also provides a silicon wafer having a resistivity of 100 xcexa9xc2x7cm or more, an interstitial oxygen concentration of 8 ppma or less and a bulk defect density of 1xc3x97108 to 2xc3x971010 defects/cm3.
Such a silicon wafer having a high resistivity of 100 xcexa9xc2x7cm or more, an interstitial oxygen concentration of 8 ppma or less and a bulk defect density of 1xc3x97108 to 2xc3x971010 defects/cm3 as mentioned above can be a silicon wafer in which high resistivity is maintained even after the wafer is subjected to a low temperature heat treatment at 350 to 500xc2x0 C. such as a device heat treatment, and which has sufficient gettering effect.
The present invention also provides a bonded SOI wafer which utilizes the high resistivity CZ silicon wafer of the present invention as a base wafer.
Such a bonded SOI wafer which utilizes the CZ silicon wafer of the present invention as a base wafer is an SOI wafer in which high resistivity is maintained even after a device production heat treatment, and which has gettering effect. Therefore, it can be made with a larger diameter, and it can reduce the signal transmission loss and so forth. Thus, it is especially useful for high-frequency devices.
The oxygen precipitation heat treatment to which the base wafer for the bonded SOI wafer is subjected can also serve as a bonding heat treatment used in the production process of the bonded SOI wafer.
That is, in the production of the bonded SOI wafer comprising a step of bringing a bond wafer into close contact with a base wafer via an oxide film, a step of subjecting them to a bonding heat treatment so that the both should be firmly bonded, and a step of making the bond wafer into a thin film as an SOI layer, if a silicon wafer having a resistivity of 100 xcexa9xc2x7cm or more and an initial interstitial oxygen concentration of 10 to 25 ppma is used as the base wafer, and such a heat treatment that can provides a residual interstitial oxygen concentration in the base wafer of 8 ppma or less is performed as the bonding heat treatment, an SOI wafer having both of high resistivity and sufficient gettering effect can be produced more efficiently.
In this case, the base wafer to be used may be a wafer subjected to at least a part of the oxygen precipitation heat treatment before the step of bringing the bond wafer into close contact with the base wafer.
When a multi-step heat treatment is performed as the oxygen precipitation heat treatment performed during the production process of a bonded SOI wafer, a part of the oxygen precipitation heat treatment can be performed beforehand for a base wafer before it is brought into close contact with a bond wafer, and the remaining heat treatment can be performed as the bonding heat treatment. If the oxygen precipitation heat treatment required for the production process of a bonded SOI wafer is performed as divided heat treatments, the bonding heat treatment process can be shortened compared with the case where it is attained only by the bonding heat treatment. Therefore, the time control of each step becomes easy, thus stock between process steps can be reduced, and products can be produced efficiently.
Furthermore, in the above case, at least a part of the oxygen precipitation heat treatment performed for the base wafer can also be performed before the final polishing of the base wafer.
While at least a part of the oxygen precipitation heat treatment performed for a base wafer before the step of bringing the base wafer into close contact with the bond wafer may be performed after the base wafer is mirror-polished, it is preferably performed before the final polishing of the polishing process. If at least a part of the oxygen precipitation heat treatment before the close contacting step is performed before the final polishing as described above, degradation of microroughness, haze or the like of a surface of the wafer possibly caused by the heat treatment process can be improved by the final polishing, and thus occurring frequency of bonding defect (void) can be suppressed.
Furthermore, in order to achieve the aforementioned second object, the present invention provides a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having an initial interstitial oxygen concentration of 10 to 25 ppma by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to an oxygen precipitation heat treatment so that a residual interstitial oxygen concentration in the wafer should become 8 ppma or less. In this method, it is preferable to perform the oxygen precipitation heat treatment so that a residual interstitial oxygen concentration in the wafer should become 6 ppma or less.
By subjecting a CZ wafer obtained from a silicon single crystal ingot having an initial interstitial oxygen concentration of 10 to 25 ppma to an oxygen precipitation heat treatment so that a residual interstitial oxygen concentration in the wafer should become 8 ppma or less, preferably 6 ppma or less as described above, oxide precipitates and residual interstitial oxygen necessary for suppressing slip dislocations can be formed in the bulk portion of the wafer.
Further, by producing a silicon wafer as described above, the anti-slip property of a portion to be contact with a heat treatment boat in a CZ wafer to be subjected to the subsequent heat treatment is improved, and a silicon wafer containing substantially no slip generated from oxide precipitates themselves can be produced through a relatively simple and practical method.
Furthermore, in the aforementioned method, the oxygen precipitation heat treatment is preferably carried out by performing a high temperature heat treatment at 1100xc2x0 C. or higher in the first step to out-diffuse the interstitial oxygen in the surface of the wafer, so that a DZ layer (Denuded Zone) should be formed in the wafer surface.
By performing such an oxygen precipitation heat treatment, there can be obtained a wafer in which slip dislocations hardly occur and which has superior gettering characteristic, and moreover oxide precipitates in the wafer surface are reduced. Therefore, when devices are formed on the surface, the possibility of adverse effect on the device characteristics is substantially eliminated.
Further, also in a case where an epitaxial layer is formed on the surface of the wafer produced according to the present invention, it is preferable to perform a heat treatment so that a DZ layer should be formed as described above, since there is little possibility that crystallinity of the epitaxial layer is degraded if a DZ layer is formed on the wafer surface.
Furthermore, according to the present invention, when a silicon wafer is produced by performing the oxygen precipitation heat treatment, the oxygen precipitation heat treatment for the silicon wafer is preferably performed before the final polishing of the wafer.
The oxygen precipitation heat treatment of the present invention may be performed for a mirror-polished wafer. However, if it is performed for a wafer having a chemically etched surface (CW) before it is subjected to the mirror polishing, or a wafer before it is subjected to a final polishing of the polishing process of the wafer, which is usually comprises multiple steps (for example, primary polishing, secondary polishing and polishing for finishing (final polishing)), there can be obtained an advantage that possible degradation of surface conditions of the wafer in the oxygen precipitation heat treatment process can be improved in the subsequent polishing.
The present invention further provides a silicon wafer produced by the aforementioned production method. A silicon wafer produced as described above is a silicon wafer that shows superior anti-slip property and gettering characteristic, and produces extremely few slip dislocations or defects during a heat treatment process in the device production and the like.
Further, since it shows high anti-slip property, slip can be suppressed without lowering the conventional process temperature. Therefore, the applicable range of the device process is broadened, and extremely useful silicon wafers can be provided.
The present invention also provides a silicon wafer having an interstitial oxygen concentration of 8 ppma or less and an oxide precipitate density of 1xc3x97108 to 2xc3x971010 precipitates/cm3 in the wafer. The interstitial oxygen concentration is preferably 6 ppma or less, and to put it concretely, the oxide precipitates in the silicon wafer are polyhedrons having a size of 200 nm or more or plates having a size of 230 nm or more.
This wafer can also suppress the generation of slip dislocations during the gettering heat treatment at a high temperature or device production heat treatment to be performed subsequently, and there can be obtained a wafer exhibiting superior gettering characteristic and extremely suitable for the production of LSI and so forth.
The present invention also provides an epitaxial wafer comprising an epitaxial layer formed on the surface of the aforementioned silicon wafer.
An epitaxial wafer in which an epitaxial layer is formed on the silicon wafer of the present invention can be an epitaxial wafer that is not hitherto known, in which the generation of slip dislocations in the epitaxial step is suppressed, and which has also high resistivity and gettering effect. Therefore, the application thereof is broadened over various devices.
As explained above, according to the present invention, a CZ silicon wafer having a resistivity of 100 xcexa9xc2x7cm or more is subjected to the oxygen precipitation heat treatment so that the residual interstitial oxygen concentration should become 8 ppma or less, and this enables preventing the reduction of resistivity due to the generation of oxygen donors occurring during a heat treatment in the device production process, in particular, a device production heat treatment at 350 to 500xc2x0 C. performed in the electrode wiring process and so forth and providing a high resistivity CZ wafer also exhibiting high gettering effect. In addition, this wafer can be used as it is, but also as a base wafer of a bonded SOI wafer, and it can be easily produced with a larger diameter. Moreover, wafers showing little signal transmission loss and so forth can be produced with high productivity.
Furthermore, according to the present invention, a CZ silicon wafer is subjected to the oxygen precipitation heat treatment so that the residual interstitial oxygen concentration should become 8 ppma or less, thereby the anti-slip property of a portion to be in contact with a heat treatment boat in a CZ silicon wafer to be subjected to the subsequent heat treatment is improved, and a silicon wafer containing substantially no slip generated from oxide precipitates themselves can be produced through a relatively simple and practical method.
Therefore, by using such a wafer, slip can be sufficiently suppressed, even if the wafer is a wafer having a large diameter of 200 mm, 300 mm or more, which is likely to suffer from the generation of slip dislocation. In addition, since the wafer exhibits high anti-slip property, slip can be suppressed without lowering the conventional process temperature. Therefore, the applicable range of the device process is broadened, and extremely useful silicon wafers can be provided.